1. Field of the Invention
The present invention relates to an IC testing device and, more particularly, to an IC testing device that makes effective use of hardware to apply a test signal waveform to I/O pins and input-dedicated pin of an IC under test and measure response signals from its I/O pins and output-dedicated pins.
2. Background of the Related Art
In an IC test a test signal is applied to a signal input terminal pin of an IC under test (hereinafter referred to as a DUT) and a check is made to determine if its response signal is at a voltage and timing within prescribed ranges and has an expected logical value. In this instance, test signals of different waveforms (i.e. different voltages and timing, for instance) are applied to the DUT and its response signals to various test signals are measured. The DUT usually has a large number of terminal pins such as pins serving also as input/output terminals (I/O pins), input-dedicated pins (I-dedicated pins) and output-dedicated pins (O-dedicated pins). For example, in a conventional IC testing device of FIG. 1, a format control circuit 5 of each measurement circuit 8 sets the waveform (waveform, voltage, timing, etc.) of the test signal to be applied to a DUT 2 and applies it to an I/O pin or I-dedicated pin of the DUT 2 via a driver 3, an I/O transmission line 7, an I/O terminal 11 and an I/O transmission line 12 on a performance board 10. An output signal from the DUT 2, which is provided in response to the application thereto of the test signals, is applied to an analog comparator 4 from an I/O terminal pin 13 and an O terminal pin 15 via transmission lines 12, 19 and 7. The analog comparator 4 makes a logical decision of the response signal by comparing it with a reference voltage and provides the decision result to a digital comparator 6, wherein it is compared with a digital expected value, and the comparison result is written in a memory (not shown) of the testing device.
A pin electronics card 1 of the IC testing device has, in pairs of a number necessary for device testing (the number of pins, for instance), drivers 3 each for applying the test signal to the DUT 2 and analog comparator 3 each for making a logical decision of the response signal from the DUT 2. The IC testing device configuration falls roughly into an I/O common system shown in FIG. 1 in which the driver 3 and the analog comparator 4 of each measurement circuit 8 are connected in the pin electronics card 1 so that the measurement circuit 8 is connected to the pins of the DUT 2 via a single line on the performance board 10 and an I/O split system shown in FIG. 2 in which the driver 3 and the analog comparator 4 of each measurement circuit 8 are not connected in the pin electronics card 1 so that the measurement circuit 8 is connected to the I/O terminal of the DUT 2 via two lines on the performance board 10. The merits and demerits of the both systems depend on pin specifications of the DUT 2, that is, the ratios of the numbers of I-dedicated and O-dedicated pins to the number of I/O pins.